TUT has developed several generations of reconfigurable arrays. The latest ones are template architectures, to be instantiated in different dimensionality (e.g. 4x4, 8x4, 8x8, 8x9, 16x4, …) and with different functionality and interconnect networks. The processing elements (PEs) of the arrays are capable to perform 32-bit fixed-point or floating-point operations. The execution on the array is controlled by configuration memories, where one or several contexts can be uploaded by a host processor. The contexts define the “data flow graph” that the array is implementing, i.e., the functions of the PEs and how they are interconnected. The benefit of CGRAs compared to FPGA is that the reconfiguration time is very short, as the number of controllable elements is small. Also the design can be done on high level, as word-level arithmetic is used. The latter feature can also be exploited by using the CGRA architecture as an overlay on top of an FPGA. CGRAs can also be integrated on ASIC to gain full benefit of their application-specific nature.